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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max2310/max2312/max2314/MAX2316 are if receivers designed for dual-band, dual-mode, and sin- gle-mode n-cdma and w-cdma cellular phone sys- tems. the signal path consists of a variable gain amplifier (vga) and i/q demodulator. the devices fea- ture guaranteed +2.7v operation, a dynamic range of over 110db, and high input ip3 (-33dbm at 35db gain, 1.7dbm at -35db). unlike similar devices, the max2310 family of receivers includes dual oscillators and synthesizers to form a self-contained if subsystem. the synthesizers refer- ence and rf dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architec- tures using any common reference and if frequency. the differential baseband outputs have enough band- width to suit both n-cdma and w-cdma systems, and offer saturated output levels of 2.7vp-p at a low +2.75v supply voltage. including the low-noise voltage-con- trolled oscillator (vco) and synthesizer, the max2310 draws only 26ma from a +2.75v supply in cdma (dif- ferential if) mode. the max2310/max2312/max2314/MAX2316 are avail- able in 28-pin qsop packages. applications single/dual/triple-mode cdma handsets globalstar dual-mode handsets wireless data links tetra direct-conversion receivers wireless local loop (wll) features ? complete if subsystem includes vco and synthesizer ? supports dual-band, triple-mode operation ? vga with >110db gain control ? quadrature demodulator ? high output level (2.7v) ? programmable charge-pump current ? supports any if frequency between 40mhz and 300mhz ? 3-wire programmable interface ? low supply voltage (+2.7v) max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ________________________________________________________________ maxim integrated products 1 19-1507; rev 0a; 8/99 part max2310 eei max2312 eei -40c to +85c -40c to +85c temp. range pin-package 28 qsop 28 qsop evaluation kit manual follows data sheet pin configurations appear at end of data sheet. block diagram appears at end of data sheet. ordering information selector guide max2314 eei MAX2316 eei -40c to +85c -40c to +85c 28 qsop 28 qsop single band, dual mode amps, cellular cdma max2314 single band, single mode pcs cdma dual band, triple mode amps, cellular cdma, pcs cdma max2310 max2312 description mode part single band, single mode or single band, dual mode with external discriminator cellular cdma MAX2316 40mhz to 150mhz 40mhz to 150mhz 67mhz to 300mhz 40mhz to 300mhz input range
i cc max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +2.7v to +5.5v, mode = divsel = shdn = stby = bufen = high, differential output load = 10k , t a = -40c to +85c, registers set to default power-up settings. typical values are at v cc = +2.75v and t a = +25c, unless otherwise noted.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..............................................................-0.3v, +6.0v shdn to gnd.............................................-0.3v to (v cc + 0.3v) stby , bufen , mode, en, data, clk, divsel ...........................................-0.3v to (v cc + 0.3v) vgc to gnd...............-0.3v, the lesser of +4.2v or (v cc + 0.3v) ac signals tankh , tankl , ref, fm , cdma .................................................1.0v peak digital input current shdn , mode, divsel, bufen , data, clk, en , stby .....................................10ma continuous power dissipation (t a = +70c) 28-pin qsop (derate 10mw/c above t a = +70c) ....800mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-65c to +160c lead temperature (soldering, 10sec) .............................+300c v cc = 2.75v cdma mode i+ to i- and q+ to q-, pll locked 50k load 50k load shdn = low 0.5v < v vgc < 2.3v addition for lo out ( bufen = low) conditions v v cc - 1.4 common-mode output voltage mv -20 1.5 +20 dc offset voltage v 0.5 lock indicator low (unlocked) v 2.0 lock indicator high (locked) a 1 vgc control input current during shutdown a -5 5 vgc control input current a 2 i il logic low input current 41.5 25.9 37.5 a 2 i ih logic high input current v 0.5 logic low v 2.0 logic high ma 3 5.8 i cc register shutdown current 3.5 units min typ max symbol parameter t a = +25c t a = -40c to +85c i cc supply current (note 1) ma t a = +25c t a = -40c to +85c fm iq mode 40.6 25.4 36.7 t a = +25c t a = -40c to +85c fm i mode 39.5 24.7 35.7 t a = +25c t a = -40c to +85c standby (vco_h) 20.7 12.3 18.8 t a = +25c t a = -40c to +85c standby (vco_l) 20.3 11.5 18.4 shdn = low a 1.5 10 i cc shutdown current
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 3 ac electrical characteristics (max2310/max2314 or max2312/MAX2316 ev kit, v cc = +2.75v, registers set to default power-up states, f in = 210.88mhz for cdma, f in = 85.88mhz for fm, f ref = 19.68mhz, synthesizer locked with passive 2nd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k , all power levels referred to 50 , t a = +25c, unless otherwise noted.) (note 2) (note 2) gain = +35db (note 5) gain = -35db gain = +35db gain = -35db gain = -35db (note 3) gain = +35db (note 4) conditions dbm -31 iip3 input third-order intercept -6.0 db 6.36 nf dsb noise figure 62.9 db 56 61.3 a v maximum voltage gain db -54.8 -49 a v minimum voltage gain vp-p 0.2 v ref frequency reference signal level mhz 39 f ref mhz 40 300 f in input frequency reference frequency dbm -49 input 0.25db desensitization -14.8 dbm -44 -38.3 p 1db input 1db compression -9 -6.4 1.7 dbm -33.2 iip3 input third-order intercept units min typ max symbol parameter (notes 6, 8) dbm -44 -38.4 p 1db input 1db compression -20 -16.2 db 58.5 63.4 a v maximum voltage gain db -50.2 -47.4 a v minimum voltage gain mhz 4.2 normalized to +25c baseband 0.5db bandwidth differential t a = t min to t max vp-p 2.7 v sat saturated output level mvp-p db 2.5 maximum gain variation over temperature 1 lo to baseband leakage db +30 +35 quadrature suppression r l = 50 , bufen = low (note 2) dbm -13.7 p lo loout output power mhz 135 600 f vco_h vco tune range 80 300 f vco_l signal path, cdma mode signal path, fm_iq mode signal path, cdma and fm_iq mode phase-locked loop gain = +35db v gc = 0.5v (note 6) gain = -35db gain = -35db v gc = 0.5v (note 6) gain = -35db gain = +35db (note 7) gain = +35db v gc = 2.3v (note 6) v gc = 2.3v (note 6)
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (max2310/max2314 or max2312/MAX2316 ev kit, v cc = +2.75v, registers set to default power-up states, f in = 210.88mhz for cdma, f in = 85.88mhz for fm, f ref = 19.68mhz, synthesizer locked with passive 2nd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k , all power levels referred to 50 , t a = +25c, unless otherwise noted.) 120khz offset 30khz offset -119 12.5khz offset 1khz offset (note 6) (note 6) conditions -110 30khz offset 12.5khz offset -105 1khz offset 900khz offset -91 -100 -72 dbc -50 base band spurious due to pll -64 dbc/hz -125 loout at 85mhz, vco_l enabled (note 9) 900khz offset khz 1500 maximum phase detector comparison frequency khz 20 minimum phase detector comparison frequency 2047 r1, r2 ref maximum divide ratio 2 r1, r2 ref minimum divide ratio 16383 m1, m2 vco maximum divide ratio dbc/hz -125 256 m1, m2 vco minimum divide ratio units min typ max symbol parameter 120khz offset loout at 210mhz, vco_h enabled (note 9) locked, cpx = 00 acquisition, cpx = xx, tc = 1 105 150 190 -115 1480 2100 2650 charge-pump source/sink current note 1: fm_iq and fm_i modes are not available on max2312 and MAX2316. note 2: recommended operating frequency range. note 3: f 1 = 210.88mhz, f 2 = 210.89mhz, p f1 = p f2 = -15dbm. note 4: f 1 = 210.88mhz, f 2 = 210.89mhz, p f1 = p f2 = -50dbm. note 5: small-signal gain at 200khz below the lo frequency will be reduced by less than 0.25db when an interfering signal at 1.25mhz below the lo frequency is applied at the specified level. note 6: guaranteed by design and characterization. note 7: f 1 = 85.88mhz, f 2 = 85.98mhz, p f1 = p f2 = -15dbm. note 8: f 1 = 85.88mhz, f 2 = 85.98mhz, p f1 = p f2 = -50dbm. note 9: measured at loout with bd = 0 ( ? 2 selected). locked, cpx = 10 locked, cpx = 01 210 300 380 150 210 265 locked, all values of cpx, 0.5v < v cp < v cc - 0.5v locked, cpx = 11 % 0.2 10 charge-pump source/sink matching a 300 425 530 turbo lock
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 5 20.00 25.00 22.50 30.00 27.50 32.50 35.00 2.5 3.5 4.0 3.0 4.5 5.0 5.5 receive supply current vs. supply voltage max2310 toc01 supply voltage (v) supply current (ma) t a = +85? t a = +25? t a = -40? 0 0.004 0.002 0.008 0.006 0.012 0.010 0.014 2.0 3.0 3.5 2.5 4.0 4.5 5.0 5.5 receive shutdown current vs. supply voltage max2310 toc02 supply voltage (v) shutdown current (ma) t a = -40? t a = +25? t a = +85? -80 -60 -40 -20 0 20 40 60 80 0.5 1.0 1.5 2.0 2.5 3.0 gain vs. v gc nax2310 toc03 v gc (v) gain (db) t a = +25? t a = -40? t a = +85? 15 25 20 35 30 40 45 55 50 60 0 100 200 300 400 500 gain vs. input frequency max2310 toc04 frequency (mhz) gain (db) v gc = 2.5v 56.0 57.0 56.5 57.5 59.0 59.5 58.5 58.0 60.0 0 46810 2 1214161820 gain vs. baseband frequency max2310 toc05 frequency (mhz) relative gain (db) -60 -40 -50 -20 -30 0 -10 10 -60 -20 0 -40 20 40 60 80 third-order input intercept vs. gain max2310 toc06 gain (db) iip3 (dbm) t a = -40? t a = +85? t a = +25? 0 60 20 10 30 40 50 70 -40 -20 -10 0 -30 10 20 50 40 60 30 70 noise figure vs. gain max2310 toc07 gain (db) nf (db) 6.0 6.4 6.2 6.8 6.6 7.2 7.0 7.4 -40 0 20 -20 40 60 80 100 noise figure vs. temperature max2310 toc08 temperature (?) nf (db) lock vco voltage vco voltage vs. time max2310 toc09 time (500 m s/div) volts (1v/div) shdn lock time 1.83ms typical operating characteristics (max2310/max2314 or max2312/MAX2316 ev kit, v cc = +2.75v, registers set to default power-up states, f in = 210.88mhz for cdma, f in = 85.88mhz for fm, f ref = 19.68mhz, synthesizer locked with passive 2nd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k , all power levels referred to 50 , t a = +25c, unless otherwise noted.)
pin description max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 6 _______________________________________________________________________________________ fm port s11 vs. frequency max2310 toc10 1: 641 - j428 10mhz 2: 27 - j162 85mhz 3: 4 - j73 210mhz 4: 1.8 - j39 600mhz 1 4 2 3 tankl port 1/s11 vs. frequency max2310 toc11 1: -3.06ms + j349 m s, 100mhz 2: -3.01ms + j853 m s, 160mhz 3: -3.11ms + j1.45ms, 240mhz 4: -3.04ms + j1.85ms, 300mhz 2 3 4 1 tankh port 1/s11 vs. frequency max2310 toc12 1: 1.98ms + j437?, 100mhz 2: 2.18ms + j853?, 160mhz 3: 2.11ms +j 2.53ms, 420mhz 4: 2.17ms +j 3.71ms, 600mhz 4 3 2 1 typical operating characteristics (continued) (max2310/max2314 or max2312/MAX2316 ev kit, v cc = +2.75v, registers set to default power-up states, f in = 210.88mhz for cdma, f in = 85.88mhz for fm, f ref = 19.68mhz, synthesizer locked with passive 2nd-order lead-lag loop filter, shdn = high, vgc set for +35db voltage gain, differential output load = 10k , all power levels referred to 50 , t a = +25c, unless otherwise noted.) loout port s22 vs. frequency max2310 toc13 1: 108.63 w (re) 10.266 w (1m) 40mhz 2: 134.99 w (re) 13.71 w (1m) 150mhz 3: 158.83 w (re) 39.58 w (1m) 300mhz cdma port s11 vs. frequency max2310 toc14 1: 10mhz, 375 w - j56 w 2: 85mhz, 285 w - j200 w 3: 210mhz, 73 w - j169 w 4: 600mhz, 2.1 w - j34 w 1 4 2 3 MAX2316 max2314 pin name 1 1, 8 byp bypass node. must be capacitively decoupled (bypassed) to analog ground. 1 1 2 2 cp_out charge-pump output 2 2 3 3 gnd analog ground reference 3 3 5, 6 4, 5 tankl+, tankl- differential tank input for low-frequency oscillator 4, 5 4 divsel high selects m1/r1; low selects m2/r2. 4 max2312 max2310 function
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 7 pin description (continued) 27, 28 27, 28 bypass node. must be capacitively decoupled (bypassed) to analog v cc . byp 27, 28 27, 28 23, 24 23, 24 differential cdma input. active in cdma mode. cdma-, cdma+ 23, 24 23, 24 25 differential positive input. active in fm mode. fm+ 25 22 22 vga gain control input. control voltage range is 0.5v to 2.3v. vgc 22 22 20 20 data input of the 3-wire serial bus. data 20 20 19 19 enable input. when low, input shift register is enabled. en 19 19 18 18 clock input of the 3-wire serial bus clk 18 18 16, 17 16, 17 differential quadrature-phase baseband output. disabled if fm_i mode is selected. qout-, qout+ 16, 17 16, 17 15 15 lock outputopen-collector pin. logic high indicates phase- locked condition. lock 15 15 13, 14 13, 14 differential in-phase baseband output, or fm signal output fm_i mode is selected. iout+, iout- 13, 14 13, 14 12 12 shutdown inputactive low. low powers down entire device, including registers and serial interface. shdn 12 12 11 11 reference frequency input ref 11 11 8 internal vco output. depending on setting of bd bit, loout is either the vco frequency (twice the if frequency) or one- half the vco frequency (equal to the if frequency). loout 8 6, 7 5, 6 differential tank input for high-frequency oscillator tankh+, tankh- name function pin max2310 max2312 max2314 MAX2316 7 lo buffer amplifieractive low bufen 7 no connection. must be left open-circuit. n.c. 6, 7 8 mode select. high selects cdma mode; low selects fm mode. mode 10 10 digital ground gnd 10 10 9 9 +2.7v to +5.5v supply for digital circuits v cc 9 9 21 21 2.7v to 5.5v supply for analog circuits v cc 21 21 26 differential negative input for fm signal. bypass to gnd for single-ended operation. fm- 26 26 standby inputactive low. low powers down vga and demod- ulator while keeping vco, pll, and serial bus on. stby 26 25 no connection. n.c. 25
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 8 _______________________________________________________________________________________ _______________detailed description max2310 the max2310 is intended for dual-band (pcs and cel- lular) and dual-mode code division multiple access (cdma) and fm applications (figure 1). the device includes an if variable-gain amplifier, quadrature demodulator, dual vcos, and dual-frequency synthe- sizers (figure 7). dual vcos are provided for applica- tions using different if frequencies for each mode or band of operation. the analog fm output signal can be configured for conversion to the i channel, or it may be converted in quadrature to both the i and q channels. the max2310s operation modes are described in table 1. these modes are set by programming the con- trol register and setting logic levels on control pins. if mode is left floating, the internal register controls the operation. if driven high or low, mode will override cer- tain register bits, as shown in table 1. max2310 byp byp fm- fm+ cdma+ cdma fm 3-wire dac 0.1 m f 0.01 m f 0.033 m f 47pf 5pf 18pf 3.3nf 10k 10k 10k 18pf 47pf 68nh 0.01 m f 680 w cdma- lock vgc v cc v cc v cc v cc data clk qout+ qout- en tankh- iout- iout+ ref gnd v cc mode tankh+ tankl- gnd cpout byp shdn tankl+ 0.01 m f v cc 47pf 10k 47k q i 10k 1.5pf 12pf 10k 10k 12pf 18nh figure 1. max2310 typical operating circuit
m s b max2312/MAX2316 the max2312/MAX2316 quadrature demodulators are simplified versions of the max2310 that can be used in single-mode cdma or dual mode using an external fm discriminator (figures 2a and 2b). the max2312 vco is optimized for the 67mhz to 300mhz if frequency range, while the MAX2316 vco is optimized for the 40mhz to 150mhz if frequency range. both devices include a buffered output for the vco. the buffered vco output can be used to support sys- tems implementing traditional limiting if stages for fm demodulation in dual-mode phones as well as for the transmit lo in tdd systems. this buffered output can be configured for the vco frequency (twice the if fre- quency) or one-half the vco frequency (if frequency). the bufen pin enables this feature. a standby mode, in which only the vco and synthesizer are operational, can be selected through the serial interface or the stby pin. the max2312/MAX2316s operational modes are described in table 2. these modes are set by pro- gramming the control register and/or setting logic lev- els on control pins. if the control pins ( stby , bufen , divsel) are left floating, the internal register controls the operational mode. if driven high or low, the control pins will override certain register bits, as shown in table 2. max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer _______________________________________________________________________________________ 9 table 1. max2310 control register states mode shdn pins x l shutdown pin completely powers down the chip shutdown action result operational mode test_mode x cp pol test_en x x turbocharge divsel x vco_byp vco_sel x x x buf_div bufen x x fm_type in_sel x stby shdn ml s control register s bb x x x x x x h x 0 in shutdown register bit leaves serial port active shutdown x x x x x x x 0 x x x 0 x h x 0 in standby register bit turns off vga and modulator only standby x x 1 0 0 h h mode pin overrides vco_sel, divsel, and in_sel to high cdma x x x x x 1 x 1 0 f h floating mode pin returns control to register cdma 1 1 x x 1 1 x 1 0 l h mode pin overrides vco_sel, divsel, and in_sel to low fm_iq x x x x x 1 0 1 0 f h floating mode pin returns control to register fm_iq x x 0 1 0 1 0 l h mode pin overrides vco_sel, divsel, and in_sel to low fm_i x x x x x 1 1 1 0 f h l floating pins return control to register fm_i x x 0 1 1 1 note: h = high, l = low, f = floating pin, x = dont care, blank = independent parameter, 1 = logic high, 0 = logic low.
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 10 ______________________________________________________________________________________ max2312 byp byp stby cdma+ 3-wire dac 0.01 m f 0.01 m f 47pf 1.5pf 12pf 3300pf 10k 10k 12pf 47pf 18nh 0.01 m f 680 w cdma- lock vgc v cc v cc v cc v cc v cc v cc data clk qout+ qout- en bufen iout- iout+ ref gnd v cc loout tankh- tankh+ gnd cpout byp shdn divsel 47pf 10k 47k 10k 0.033 m f 10k q i cdma figure 2a. max2312 typical operating circuit
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 11 MAX2316 byp byp stby cdma+ 3-wire dac 0.01 m f 0.01 m f 0.033 m f 47pf 5pf 17pf 3300pf 10k 10k 10k 18pf 47pf 68nh 0.01 m f 680 w cdma- lock vgc v cc v cc v cc v cc v cc v cc data clk qout+ qout- en bufen iout- iout+ ref gnd v cc loout tankl- tankl+ gnd cp_out byp shdn divsel 47pf fm 455khz 10k 10k limiter discriminator 47k q i cdma figure 2b. MAX2316 typical operating circuit
msb max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 12 ______________________________________________________________________________________ table 2. max2312/MAX2316 control register states note: h = high, l = low, 1 = logic high, 0 = logic low, x = dont care, blank = independent parameter. 1 1 1 1 0 1 x 1 x 0 x x shdn stby 1/ 0 x 0 lo buffer enable if pin is floated, then bufen register bit controls buffer h f x x 0 lo buffer enable bufen pin controls the lo buffer and overrides the bit h/ l h x 1/ 0 0 divider select if div_sel pin is float- ed, then register bit selects divider h h f x x 0 divider select div_sel pin overrides div_sel register bit h h h/ l x 0 standby 0 in standby register bit turns off vga and mod- ulator only h h/ l h x 0 standby 0 in standby pin turns off vga and modulator only l h x x x x x x x x x x shutdown 0 in shutdown register bit leaves serial bus active x h x x x x x x in_sel fm_type x bufen operational mode action result buf_div x x vco_sel vco_byp x x x divsel turbocharge x tes_ten shutdown shutdown pin com- pletely powers down the chip cp_pol x l x x test_mode pins stby x bufen shdn divsel ml s control register s bb
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 13 max2314 the max2314 supports cdma cellular-band, dual- mode operation. as with the max2310, the fm mode can be configured for conversion to the i port or quad- rature conversion to both the i and q ports (figure 3). the max2314s operational modes are described in table 3. these modes are set by programming the control register and setting logic levels on control pins. __________applications information variable-gain amplifier and demodulator the max2310 family provides a variable-gain amplifier (vga) with exceptional gain range. the max2310/ max2314 support multimode applications with dual dif- ferential inputs, selectable with the in_sel (is) control bit. on the max2310 this function can be controlled with the mode pin, which overrides the is control bit. the vgas gain is controlled over a 110db range with max2314 byp byp fm- fm+ cdma+ 3-wire dac 0.01 m f 0.01 m f 47pf 5pf 18pf 3300pf 10k 10k 18pf 47pf 68nh 0.01 m f 680 w cdma- lock vgc v cc v cc v cc v cc v cc v cc data clk q_out+ q_out- en i_out- i_out+ ref gnd v cc byp tankl- gnd cp_out byp shdn tankl+ 47pf 10k 47k 10k 0.033 m f 10k fm 0.01 m f 1000pf q cdma figure 3. max2314 typical operating circuit
m s b max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 14 ______________________________________________________________________________________ the vgc pin. the output of the vga drives the rf ports of a quadrature demodulator. the max2310/max2314 provide two types of fm demodulation, controlled by the fm_type (ft) control bit. when fm_type is 1, the signal is passed through both the i and q signal paths for subsequent lowpass filtering and a/d conver- sion at baseband. if fm_type is 0, the fm signal is passed through the i mixer only. voltage-controlled oscillator, buffers, and quadrature generation the lo signal for downconversion is provided by a voltage-controlled oscillator (vco) consisting of an on- chip differential oscillator, and an off-chip high-q reso- nant network. figure 4 shows a simplified schematic of the vco oscillator. multiband operation is supported by the max2310 with dual vcos. vco_h and vco_l are selectable with the mode pin or the vco_sel (vs) control bit. they oscillate at twice the desired lo fre- quency. for applications requiring an external lo, the vcos can be bypassed with the vco_byp (vb) control bit. the max2312/MAX2316 buffer the output of the vco and provide this signal at the loout pin. this signal is enabled by the bufen (be) control bit or by the bufen control pin. the frequency of this signal is selected by the buf_div (bd) control bit, and can be either the vco frequency or half the vco frequency. quadrature downconversion is realized by providing in- phase (i) and quadrature-phase (q) components of the lo signal to the lo ports of the demodulator described above. the quadrature lo signals are generated by dividing the vco output frequency using two latches. the appropriate latch outputs provide i and q signals at the desired lo frequency. table 3. max2314 control register states note: h = high, l = low, 1 = logic high, 0 = logic low, x = dont care, blank = independent parameter stby operational mode 1 1 1 0 x x 0 fm_i fm i operation 0 h 1 0 1 0 x x 0 fm_iq fm iq quadrature operation 0 h 1 x 1 1 x x 0 cdma cdma operation 0 h 0 1 x x 0 standby 0 in standby pin turns off vga and modulator only 0 h x x l x x x x x x shutdown 0 in shutdown register bit leaves seri- al port active x h x x x x x x ml s control register s bb shdn x in_sel fm_type x x bufen buf_div x x x vco_sel vco_byp shutdown shutdown pin completely shuts down chip divsel x l x x turbocharge test_en x cp_pol p i n shdn test_mode action result
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 15 synthesizer the vcos output frequency is controlled by an internal phase-locked-loop (pll) dual-modulus synthesizer. the loop filter is off-chip to simplify loop design for emerging applications. the tunable resonant network is also off-chip for maximum q and for system design flexibility. the vco output frequency is divided down to the desired comparison frequency with the m counter. the m counter consists of a 4-bit a swallow counter and a 10-bit p counter. a reference signal is provided from an external source and is divided down to the comparison frequency with the r counter. the two divided signals are compared with a three-state digital phase-frequency detector. the phase-detector output drives a charge pump as well as lock-detect logic and turbocharge control logic. the charge pump output (cp_out) pin is processed by the loop filter and drives the tunable resonant network, altering the vco fre- quency and closing the loop. multimode applications are supported by two indepen- dent programmable registers each for the m counter (m1, m2), the r counter (r1, r2), and the charge-pump output current magnitude (cp1, cp2). the divsel (ds) bit selects which set of registers is used. it can be over- ridden by the max2310s mode pin or the max2312/ MAX2316s divsel pin. programming these registers is discussed in the 3-wire interface and registers sec- tion. when the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the turbo feature, enabled by the turbocharge (tc) control bit. turbo functionality provides a larger charge-pump current during acquisition mode. once the vco frequency is acquired, the charge-pump out- put current magnitude automatically returns to the pre- programmed state to maintain loop stability and minimize spurs in the vco output signal. the lock detect output indicates when the pll is locked with a logic high. 3-wire interface and registers the max2310 family incorporates a 3-wire interface for synthesizer programming and device configuration (figure 5). the 3-wire interface consists of a clock, data, and enable . it controls the vco dividers (m1 and m2), reference frequency dividers (r1 and r2), and a 13-bit control register. the control register is used to set up the operational modes (table 4). the input shift is 17 data bits long and requires a total of 18 clock bits (figure 6). a single clock pulse is required before enable drops low to initialize the data bus. whenever the m or r divide register value is pro- grammed and downloaded, the control register must also be subsequently updated. this prevents turbolock from going active when not desired. the shdn control bit is notable because it differs from the shdn pin. when the shdn control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. in contrast, the shdn pin, when low, shuts down everything, including the registers and seri- al interface. see the functional diagram in figure 7. registers figure 8 shows the programming logic. the 17-bit shift register is programmed by clocking in data at the rising edge of clk. before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the clk input with en high (see figure 6). pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by a0, a1, and a2, respectively (figure 8). table 5 lists the power-on default values of all registers. table 6 lists the charge-pump current, depending on cp0 and cp1. 800 m a d1 r1 c f c f r b r l tank+ tank- r l r e r e r b figure 4. voltage-controlled oscillators
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 16 ______________________________________________________________________________________ 14-bit m1 counter 14-bit m2 counter 13-bit control register (00) data clk en m u x (010) start bit 16-bit data/address register (011) (11x) (01) vco1 vco2 cpi cp2 f ref cpout 2-bit cp1 11-bit r1 counter 2-bit cp2 11-bit r2 counter figure 5. 3-wire control block diagram msb data clock enable *sb * *start bit must be logic high. *rise and fall required prior to en going low. lsb figure 6. 3-wire interface timing diagram
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 17 cp1 cp2 m1 register m2 register r1 register r2 register logic sb shift register 1 00 14 11 11 010 011 110 tm pol te tc ds vb vs bd be ft is sb sd data clk control 2 2 2 2 2 ref fm+ fm- cdma+ cdma- iout+ vgc ft vb iout- (max2310/14) qout+ qout- lo_out (max2312/16) tankl+ vco_l mode ds 14 11 11 14 14 pol 11 2 is vs (max2310) divsel (max2312/16) tankl- tankh+ tankh- lock bd be 2 tc bufen r counter m counter lock det turbo control cp_out charge pump det sb sd (max2312/16) shdn stby vco_h 14 01 2 bias en max2310 max2312 max2314 MAX2316 figure 7. functional diagram
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 18 ______________________________________________________________________________________ table 4. control register, default state: 0b57 h, address: 110 b table 5. register defaults table 6. charge-pump control bits default register m2 4269 dec m1 10519 dec ctrl ob57 hex r2 492 dec r1 492 dec cp1 11 bin cp0 11 bin sb stby logic 0 enables standby mode, which shuts down the vga and demodulator stages, leaving the vco locked and the registers active. 1 ft fm_type active in fm mode. logic 0 selects quadrature demodulator for fm mode. logic 1 selects downconversion to i port. 1 0 3 sd shdn logic 0 enables register-based shutdown. this mode shuts down everything except the m and r latches and the serial bus. 1 0 is in_sel logic 0 selects fm input port. logic 1 selects cdma input. 1 2 be bufen logic 1 disables loout. logic 0 enables loout. 1 4 vs vco_sel logic 1 selects vco_h. logic 0 selects vco_l. 1 ds div_sel logic 1 selects m1/r1 divide ratios. logic 0 selects m2/r2. 6 1 8 bd buf_div logic 1 selects divide-by-2 on loout port. logic 0 bypasses divider. 0 5 vb vco_byp logic 1 bypasses the vco inputs for external vco operation. 0 7 te test_enable must be 0 for normal operation. 0 10 tc turbo_charge logic 1 activates turbocharge mode, which provides rapid fre- quency acquisition in the pll. 1 9 pol cp_pol logic 1 causes the charge-pump output cp_out to source cur- rent when f ref /r > f vco /m. this state is used when the vco tune polarity is such that increasing voltage produces increasing fre- quency. logic 0 causes cp_out to source current when f vco /m > f ref /r. this state is used when increasing tune voltage causes the vco frequency to decrease. 1 11 bit name function bit id tm test_mode must be 0 for normal operation. 0 12 bit location 0 = lsb power- up state charge-pump current after acquisition (a) cp1 0 210 0 150 cp0 1 0 1 0 1 425 1 300
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 19 cp 2/0 cp 1/1 cp 1/0 r 1/10 cp 2/1 /1 r 2/10 m 1/0 m 1 13 m 2 13 m 2/0 a 2 /m 0 a 1 a 0 a 2 /m 0 a 1 a 0 cp2 and r2 registers shift register m1 register m2 register cp1 and r1 registers ctrl register address decoded start bit 1 00 1 0 0 1 0 1 1 1 0 r 1/0 r 2/0 0 1 tm pol te tc ds vb vs bd be ft is sb sd data figure 8. programming logic
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 20 ______________________________________________________________________________________ pin configurations bufen 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 byp byp fm- fm+ cdma+ cdma- lock vgc v cc data clk qout+ qout- iout- iout+ ref gnd v cc mode tankh- tankh+ tankl- tankl+ gnd cp_out byp qsop top view en shdn max2310 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 byp byp fm- fm+ cdma+ cdma- lock vgc v cc data clk qout+ qout- iout- iout+ ref gnd v cc byp n.c. n.c. tankl- tankl+ gnd cp_out byp qsop en shdn max2314 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 byp byp n.c. cdma+ cdma- lock vgc v cc data clk qout+ qout- iout- iout+ ref gnd v cc loout tankh- tankh+ divsel gnd cpout byp qsop en shdn max2312 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 byp byp stby n.c. cdma+ cdma- lock vgc v cc data clk qout+ qout- iout- iout+ ref gnd v cc loout tankl- tankl+ divsel gnd cp_out byp qsop en shdn MAX2316 stby stby bufen
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer ______________________________________________________________________________________ 21 transistor count: 6422 chip information byp byp fm- fm+ cdma+ dac cdma- lock vga avcc v cc data clk qout+ qout- en tankh- iout- iout+ ref dv cc mode tankh+ tankl- agnd cp_out byp shdn tankl+ /2 0 90 charge pump phase detector /r /m max2310 v cc block diagram
max2310/max2312/max2314/MAX2316 cdma if vgas and i/q demodulators with vco and synthesizer 22 ______________________________________________________________________________________ package information qsop.eps

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